[Coladam] Adam FDC Work

Geoff Oltmans oltmansg at gmail.com
Wed Jul 25 00:39:50 CEST 2012


John: I've got my own set of notes so I can compare with that. The one shot as I understand from comparing the data sheets is that there would not have been enough setup and hold time otherwise for the fdc chip. The E signal is really intended for 68xx/65xx peripherals so they modified it with the one shot.

Sent from my iPhone

On Jul 24, 2012, at 11:55 AM, John Turner <gimechip at live.com> wrote:

> 
> So, after I laid out an initial prototype for a replacement FDC (using a CPLD, WD1773 and MC6803 with SRAM and EPROM), I needed to know the mapping of the Coleco FDC controller board. A quick look at the schematic gave me the rather strange memory map of this device. I thought perhaps others might find these notes useful, so I have copied and pasted my notes below. Those in the know - if you spot anything wrong in that which follows, please let me know, as I plan to order a prototype PCB soon but I'd like to make sure I haven't overlooked anything. Note that the device as I have designed it is powered by an ATX power supply and the controller board can thus also power the Adam in the absence of the printer. - John
> 
> ***********************
> 
> ADAM Floppy Disk Drive Notes:
> =========================
> 2793 FDC Chip Mapping in the 680x Address Space:
> CA0 = A13
> CA1 = A14
> !RE = A12=0, E=1, A15=0
> !WE = E=1, A12=1 {After a 400nS delay}
> !CS = A11=1, A15=0
> 
> READ ADDRESSES:
> $0800 - STATUS REGISTER
> $2800 - TRACK REGISTER
> $4800 - SECTOR REGISTER
> $6800 - DATA REGISTER
> WRITE ADDRESSES:
> $1800 - COMMAND REGISTER
> $3800 - TRACK REGISTER
> $5800 - SECTOR REGISTER
> $7800 - DATA REGISTER
> 
> A12 SORT OF ACTS AS AN !R/W SIGNAL FOR THE FDC CHIP...
> ODDLY ENOUGH - THE R/!W LINE FROM THE 680X CHIP WAS NOT UTILIZED, WHICH
> IS WHY A 400nS DELAY IS NEEDED VIA THE ONE-SHOT - THAT'S JUST STRANGE TO ME - ALMOST AS STRANGE AS THE MAPPING OF THE FDC CHIP ITSELF...
> -----------------------------------------------------------------------------------------------------------------
> 
> Adam FDC ROM Chip map:
> ======================
> !OE = A15=1, E=1
> A0-A11 TO EPROM A0-A11
> A12, A13, A14 = NOT USED
> 
> This puts the ROM chip at $8000 and mirrors it to the end of memory. The rom is 4K and is actually assumed by it's code to be in the $F000-$FFFF range, with the actual code residing in $F800-$FFFF.
> 
> --------------------------------------------------------------------------------------------------------------------
> 
> Adam FDC RAM Chip map:
> =====================
> Okay, so this is strange:
> SRAM !WE = A12 = LOW
> SRAM !S (!CE) = A10=1,E=1,A15=0
> 
> What this means is basically - to write to the RAM, you write to $0400 and up (1k total), but to read the RAM, you read from $1400 and up (1k total). So, the SRAM is mapped started at $0400 for writes and $1400 for reads.
> 
> -----------------------------------------------------------------------------------------------------------------------
> 
> I am sure Coleco's engineers probably had a reason for designing this way, but seriously - not using the R/!W line and instead using a one-shot triggered by the E clock to create a write enable signal? I cannot understand the reasoning there - that's just another analog adjustment required in a digital device...
> 
> Anyway, at least I have the map of the hardware so I can program the CPLD in my prototype to emulate it...
> 
> I'll keep you posted... - John
> 
> _______________________________________________
> Coladam mailing list
> Coladam at adamcon.org
> http://adamcon.org/cgi-bin/mailman/listinfo/coladam

Sent from my iPhone

On Jul 24, 2012, at 11:55 AM, John Turner <gimechip at live.com> wrote:

> 
> So, after I laid out an initial prototype for a replacement FDC (using a CPLD, WD1773 and MC6803 with SRAM and EPROM), I needed to know the mapping of the Coleco FDC controller board. A quick look at the schematic gave me the rather strange memory map of this device. I thought perhaps others might find these notes useful, so I have copied and pasted my notes below. Those in the know - if you spot anything wrong in that which follows, please let me know, as I plan to order a prototype PCB soon but I'd like to make sure I haven't overlooked anything. Note that the device as I have designed it is powered by an ATX power supply and the controller board can thus also power the Adam in the absence of the printer. - John
> 
> ***********************
> 
> ADAM Floppy Disk Drive Notes:
> =========================
> 2793 FDC Chip Mapping in the 680x Address Space:
> CA0 = A13
> CA1 = A14
> !RE = A12=0, E=1, A15=0
> !WE = E=1, A12=1 {After a 400nS delay}
> !CS = A11=1, A15=0
> 
> READ ADDRESSES:
> $0800 - STATUS REGISTER
> $2800 - TRACK REGISTER
> $4800 - SECTOR REGISTER
> $6800 - DATA REGISTER
> WRITE ADDRESSES:
> $1800 - COMMAND REGISTER
> $3800 - TRACK REGISTER
> $5800 - SECTOR REGISTER
> $7800 - DATA REGISTER
> 
> A12 SORT OF ACTS AS AN !R/W SIGNAL FOR THE FDC CHIP...
> ODDLY ENOUGH - THE R/!W LINE FROM THE 680X CHIP WAS NOT UTILIZED, WHICH
> IS WHY A 400nS DELAY IS NEEDED VIA THE ONE-SHOT - THAT'S JUST STRANGE TO ME - ALMOST AS STRANGE AS THE MAPPING OF THE FDC CHIP ITSELF...
> -----------------------------------------------------------------------------------------------------------------
> 
> Adam FDC ROM Chip map:
> ======================
> !OE = A15=1, E=1
> A0-A11 TO EPROM A0-A11
> A12, A13, A14 = NOT USED
> 
> This puts the ROM chip at $8000 and mirrors it to the end of memory. The rom is 4K and is actually assumed by it's code to be in the $F000-$FFFF range, with the actual code residing in $F800-$FFFF.
> 
> --------------------------------------------------------------------------------------------------------------------
> 
> Adam FDC RAM Chip map:
> =====================
> Okay, so this is strange:
> SRAM !WE = A12 = LOW
> SRAM !S (!CE) = A10=1,E=1,A15=0
> 
> What this means is basically - to write to the RAM, you write to $0400 and up (1k total), but to read the RAM, you read from $1400 and up (1k total). So, the SRAM is mapped started at $0400 for writes and $1400 for reads.
> 
> -----------------------------------------------------------------------------------------------------------------------
> 
> I am sure Coleco's engineers probably had a reason for designing this way, but seriously - not using the R/!W line and instead using a one-shot triggered by the E clock to create a write enable signal? I cannot understand the reasoning there - that's just another analog adjustment required in a digital device...
> 
> Anyway, at least I have the map of the hardware so I can program the CPLD in my prototype to emulate it...
> 
> I'll keep you posted... - John
>                         
> _______________________________________________
> Coladam mailing list
> Coladam at adamcon.org
> http://adamcon.org/cgi-bin/mailman/listinfo/coladam


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